1. Field of Invention
This invention relates to semiconductor memory and, more particularly, to repairing semiconductor memory having twisted bit lines by decrementing or incrementing addresses across at least one group of word line rows of memory (i.e., a section made up of memory rows) and inverting the data within storage cells of a row at the twisted bit line boundaries to replace the defective row with a redundant row for each defective row of memory within all sections of word line rows.
2. Description of Related Art
The following descriptions and examples are not admitted to be prior art by virtue of their inclusion within this section.
Semiconductor memory is a crucial resource in modern computer systems, and is typically used for data storage and program execution. Semiconductor memory is generally connected to an execution unit by a memory bus, where the memory elements are arranged upon one or more monolithic substrates. In many computer systems, semiconductor memory can be embedded on the same monolithic substrate as that which contains the execution unit. Such embedded memory is oftentimes referred to as on-chip instruction or data cache.
Regardless of where the semiconductor memory resides relative to the execution unit, conventional memory design utilizes an array of storage cells. For example, a word line can access a row of storage cells, and information can be written to and read from separate columns of cells via bit lines.
The magnitude of voltage stored in each cell can be fairly small. The stored voltage must be detected by the change in voltage it induces on the bit line when the bit line is coupled to, for example, a storage capacitor. Any electronic noise near the bit line can induce changes in voltage on the bit line. These changes might interfere with the detection of the stored charge and, thus, lead to errors when reading information from the semiconductor memory.
There are several approaches used to minimize the effects of noise on the bit lines. For example, the semiconductor memory can be spaced from the noise source or, alternatively, the memory can be placed in an isolation well to isolate the stored charge from the noise source. Still further, the bit lines can be folded. Folded bit lines involves using two bit lines rather than one, and forming differential signals on the bit line pairs. The true and complementary bit line of each bit line pair are routed alongside each other, and any noise placed onto the bit lines is assumed to couple equally on both. Various common-mode rejection techniques attributed to the differential signal cancel the noise upon the bit line pairs so that only the voltage difference is measured.
The assumption that noise couples equally upon each of the true and complementary bit lines is not always accurate, however. Since the folded bit lines run parallel to each other across the entire array, noise from an adjacent pair might impact, for example, the true bit line more so than the complementary bit line if the true bit line is closer to that adjacent pair. A further enhancement to the folded bit line architecture was thereby devised to compensate for signal coupling from adjacent bit line pairs. This improvement is oftentimes referred to as “twisted” bit line architecture.
Twisted bit line architecture involves placing periodic twists in each bit line pair as the bit line pair proceeds across the array of cells. For example, the true and complementary bit lines of a pair are arranged so they periodically switch position with one another—i.e., are twisted. The true and complementary bit lines are thereby inverted in locations every n number of storage cells. The true bit line might start at the left-side conductor at the top of the array and, as it proceeds downward past n cells, it is routed to the right side of the pair. Conversely, the complementary bit line might start at the right side of the pair and, after traversing n cells, is routed to the left side of the pair. In the region at which the true and complementary bit lines change position (i.e., twist), a space will exist between neighboring rows of storage cells. This space will constitute a boundary between n rows and is henceforth referred to as the “twist region.”
While folded bit line and twisted bit line architectures help minimize the effects of noise placed on the low-margin signals of the bit lines, periodically switching the bit line positions proves disadvantageous when attempting to introduce redundant rows of memory cells into the array. For example, data inversion is one problem that may occur when re-mapping defective rows to redundant rows of memory when using an array having twisted bit lines. For example, if the data read from a bit line pair having the true bit line on the left side and the complementary bit line on the right side, the data will be inverted from data read from the same bit line pair with the complementary bit line on the left side and the true bit line on the right side. Depending on where the true and complementary bit lines exist for a particular row within the array relative to where the true and complementary bit lines exist within a redundant row, built-in-self-repair (BISR) will be impacted.
In an effort to account for the inversion issue, many manufacturers allocate redundant rows to each group of rows between twist regions. This BISR architecture will, therefore, allow redundancy to be taken care of “local” to the failed row. Also, since the failed row has the same bit line pair orientation as the redundant row, the data inversion problem is eliminated. However, adding redundant rows to each group of rows, where possibly numerous groups are associated with a memory array, can consume considerable layout area. The added memory array height will deleteriously increase the load attributed to each bit line. The added load will significantly degrade the overall response time of the bit line, thereby impacting the memory access time.
A BISR architecture is needed that avoids having to place redundant rows within each group of rows between twist regions. The desired BISR architecture must, however, account for the data inversion issue, yet avoid substantially increasing the overall array size. Accordingly, the improved BISR architecture must efficiently utilize the replacement rows without adding an undue number of rows within a twisted bit line array.